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8 Mbit LPC Flash
A Microchip Technology Company
SST49LF080A
Data Sheet
General Purpose Inputs Register
The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the
SST49LF080A. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME# is
brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle.
There is no default value since this is a pass-through register. See the General Purpose Inputs Regis-
ter table for the GPI_REG bits and function, and Table 9 for memory address locations for its respec-
tive device strapping.
JEDEC ID Registers
The JEDEC ID registers identify the device as SST49LF080A and manufacturer as SST in LPC mode.
See Table 9 for memory address locations for its respective JEDEC ID location.
Table 9: Memory Map Register Addresses for SST49LF080A
JEDEC ID
Device #
0 (Boot device)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Hardware Strapping ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
GPI_REG
FFBC 0100H
FFAC 0100H
FF9C 0100H
FF8C 0100H
FF3C 0100H
FF2C 0100H
FF1C 0100H
FF0C 0100H
FEBC 0100H
FEAC 0100H
FE9C 0100H
FE8C 0100H
FE3C 0100H
FE2C 0100H
FE1C 0100H
FE0C 0100H
Manufacturer
FFBC 0000H
FFAC 0000H
FF9C 0000H
FF8C 0000H
FF3C 0000H
FF2C 0000H
FF1C 0000H
FF0C 0000H
FEBC 0000H
FEAC 0000H
FE9C 0000H
FE8C 0000H
FE3C 0000H
FE2C 0000H
FE1C 0000H
FE0C 0000H
Device
FFBC 0001H
FFAC 0001H
FF9C 0001H
FF8C 0001H
FF3C 0001H
FF2C 0001H
FF1C 0001H
FF0C 0001H
FEBC 0001H
FEAC 0001H
FE9C 0001H
FE8C 0001H
FE3C 0001H
FE2C 0001H
FE1C 0001H
FE0C 0001H
T9.0 25026
?2011 Silicon Storage Technology, Inc.
16
DS25086A
11/11
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